The S3PORT40LP is a low-power reset circuit that provides following features:
Power-on Reset (POR) signal that monitors absolute value of three power supplies. POR signal includes programmable delay (during start-up only, brown-out has no assertion delay).
The POR includes internal Bandgap
Early Brown-out warning (EBW) signal that monitors absolute value of three power supplies.
Bypass Mode (BM) that enables complete override of POR signal putting the IP into low-power sleep mode,
Falling-edge-sensitive reset-signal impulse generator to notify external debug tools about reset condition from within the chip,
Test mode for easier on-chip debugging.
- 40nm TSMC Logic LP Process, 5 Metals Used (No Analog Options) with Deep-Nwell
- Power-on Reset output
- Early Warning output
- Three power domains (3.3V, 1.8V, 1.1V) monitoring
- Bandgap Included
- Reset impulse generator for external debug tools
- Bypass and Test modes
- Area Pre-shrink:0.108mm2
- Die Area Post-shrink: 0.0875mm2
- The S3PORT40LP uses threshold-detect circuits to establish the point when it is safe to operate internal circuits. This monitoring ensures that all the power supplies reaches sufficient voltage levels for correct operation.
- The POR signal may be delayed where amount of the delay is programmable via value of an external capacitor.
- The S3PORT40LP circuit is implemented in a standard 40nm lower-power process. It is readily portable across all foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- House Keeping / Auxiliary Functions
- Power supply monitoring for three power domains and reset generation
Block Diagram of the Power-on-Reset and Supply Monitoring