Movellus’ silicon-proven PLL generators plug right into our customers existing digital design flows, and delivers world class performing PLL IP in a matter of hours. The designs can be customized and re-verified in a matter of hours.
Movellus’ PLL generator is available in TSMC 28nm HPC and GF 14nm LPP process nodes. Several state of the art FinFET process nodes are currently being enabled for Movellus’ PLL generator.
Ultra-Low Power PLLs
Movellus’ architecture allows us to create nano-watt customized PLLs that are orders of magnitude smaller than traditional analog PLLs.
This enables us to satisfy the most demanding requirements for even battery-less applications for markets such as Edge AI and IoT. Our very small footprint and nano-watt power consumption features are not typically available in traditional analog PLLs.
Our fast process porting allows development on non-standard process nodes in a fraction of the time of analog PLLs. Fully digital implementation relieves voltage headroom restrictions which is not possible with analog PLLs.
Applications for Movellus’ high-performance PLL IP blocks range from complex SOC clocking to high-speed SERDES, while maintaining the simplicity and ease-of-use found in all Movellus’ designs.
Maintaining key performance metrics over a wide range of input and output frequencies allows architecture tradeoff not traditionally available to SOC designers.
Block Diagram of the PLL (Nanowatt for Edge AI, Multi-GHz for Cloud)