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Phased-locked loop 120 to 950 MHz
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integer. Frequency adjustment is carried out by using negative feedback. A phase detector compares a controlled oscillator output with a reference signal. The result is a charge pump current output that supplies external feedback filter and converted to a voltage for controlled oscillator adjustment. Switched capacitors sections is used to frequency-shift keying in a transmitting mode Clock frequency divider is used to generate a signal with frequency equal to reference frequency divided into integer number.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
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