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PCIe 3.1 PHY IP with 8GT/s uses an upgraded encoding/decoding scheme (Silicon Proven in TSMC 28HPC+)
This Peripheral Component Interconnect Express (PCIe) x4 PHY IP supports PCIe3.1 transmission. This is compliant with PCIe Rev3 Base Specification with support of PIPE 4.3 interface spec. Input clock frequency as 25Mhz, the output data rate(serial) supports all three 2.5 Gbps, 5.0 Gbps, 8.0 Gbps. 10 Pads is required and the max clock speed is 500MHz.
Operating Voltage Range :
- 0.99V-1.21V, typical=1.1V
- 2.97V-3.63V,typical=3.3V
The PHY is Silicon Proven and in Production in various applications.
Operating Voltage Range :
- 0.99V-1.21V, typical=1.1V
- 2.97V-3.63V,typical=3.3V
The PHY is Silicon Proven and in Production in various applications.
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pcie 3.1 ip IP
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support