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PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 3.1 IP supports a complete range of PCIe 3.1 Base applications and is compliant with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support 8Gbps PCIe 3.1 traffic and is backward compatible with 5.0Gbps PCIe 2.1 and 2.5Gbps PCIe 1.1 data rates. With the support of both TX and RX equalization techniques, the PCIe 3.1 IP is designed to meet the requirements of different channel conditions.
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PCI Express PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe4 Ethernet SERDES PHY - TSMC N5