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PCIe 3.0 PHY IP TSMC 28HPC

The PHY IP for PCIe 3.0 is designed according to PCIe 3.0 specification. Implemented on the TSMC 28HPC process, the PHY IP provides a cost-effective, low-power solution. The PHY IP for PCIe 3.0 operates at 8.0GTps, 5.0GTps, and 2.5GTps. The Physical Coding Sublayer (PCS) complies with the PIPE 3.0 (v0.9) and PIPE 4.2 specification, and provides support for the dynamic equalization features of PCIe 3.0. Flexibility in board design assured due to Cadence design-in kits. The PHY IP seamlessly connects to a Cadence, or third party, PIPE 3.0-compliant or PIPE 4.2-compliant controller. The PHY IP is dedicated to applications demanding low latency and high data transfer rates.

特色

BIST for manufacturing test including loopback and pattern generator, error detector, and error counter
Automatic calibration of analog circuits and offset correction
AMBA APB, JTAG and test mode interfaces for flexibility and ease of use
On-chip regulation for high jitter performance
Fully adaptive, continuous-time, linear equalizer
Programmable 3-tap transmitter FIR with polarity inversion

优势

Low-risk solution
Extensive testability - BIST, Loop back, Scan feature with JTAG, and AMBA support
Ease-of-use - System integration kit reduces system integration and signal integrity issues