NB-IoT Communications Subsystem Based on ARC EM11
The EM11D's zero-latency XY memory architecture takes advantage of instruction level parallelism and single-cycle 16+16 MAC operations to deliver power-efficient data processing. Integrated ARC Processor eXtension (APEX accelerators) for Viterbi decode and trigonometric functions provide significant reductions in cycle counts, area and power for key low-bandwidth communications kernels. A Digital Front End (DFE) interface offers seamless integration to standard NB-IoT RF transceivers.
The IoT Communications Subsystem is supported by the MetaWare Development Toolkit, which includes a rich library of DSP functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.
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