The S3DA100K12BTJ18 is a low noise voltage DAC that is ideal as a static or low speed transient reference for lownoise applications.
The voltage DAC is implemented using advanced R-2R network with optimized performance on MSB switching to prevent non-linearity issues. DAC resolution is 12 bit and maximal range is from 0V to twice the Vref voltage, so it is configurable and adaptable for required applications.
- TowerJazz 0.18μm TS18 Standard Logic Process
- 12-bit resolution
- 1.8V & 3.3V Supply Voltage
- External capacitor load
- Variable output range 0V to 2*Vref
- INL/DNL 1 LSB
- Sampling rate 100kHz
- Guaranteed output ramp speed 10V/s
- Power-Down mode
- Input reference voltage is buffered so it does not load the reference generator and the buffered reference voltage is available for the final application.
- Main feature of this DAC is low noise performance. This is achieved using low noise techniques in combination with filtering using the off-chip capacitors. Although the DAC can operate with any suitable voltage reference, it requires S3BGN3T18 or similar to guarantee the low noise levels.
- The S3DA100K12BTJ18 can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- Deliverables are subject to Agreement
- *See product datasheet for details. Terms and conditions apply.
- Low Noise Reference generation
- Low speed transients
- Auxiliary functions
Block Diagram of the Low noise 12-bit Voltage DAC