The HMAC SHA-256 Fast IP Core provides a hardware implementation of the Keyed-Hash Message Authentication Code (HMAC) for the SHA-256 hash algorithm. The Fast IP Core provides a balance between high throughput and size and comes with a 32/256-bit IO interface. The HMAC SHA-256 can accept messages up to 2^64-512 bits in length and returns a 256-bit message digest. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.
The core is designed for applications that need high throughput, low latency, and reduced power consumption.
- Implements HMAC SHA-256 keyed-hash message authentication specified by NIST FIPS 190-1
- Synchronous 32/256-bit IO interface (byte oriented)
- Pre-computation of internal key state for reduced latency
- High throughput requires only 67* clock cycles per 512-bit hash block
- Small hardware footprint for reduced power consumption
- Quick key wipe for anti-tamper applications
- Authenticated Encryption: Encrypt-then-MAC
- Cryptographic Protocols: IPSec, Data Integrity & Authenticity (TLS/SSL)
- Device specific netlist or RTL Verilog/VHDL source code
- Verilog/VHDL simulation model and testbench
- User documentation
Block Diagram of the HMAC SHA-256 Fast IP Core