Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
Floating point unit, data cache and bit manipulation extensions
a) A floating point unit
b) A data cache and
c) Bit manipulation extensions.
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Block Diagram of the Floating point unit, data cache and bit manipulation extensions

RISC-V IP
- TESIC CC EAL5+ Secure Element IP Core
- Intelligent Sensor and Power Management Design Platform
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- 64-bit embedded processor, fully compliant with the RISC-V ISA
- High performance Linux capable vector processor