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DDR3 / DDR4 / LPDDR3 / LPDDR4 Memory Controller
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OMC is the ORBITTM DDR Memory Controller, which delivers exceptional performance including high utilization & very low latency. Together with ORBITTM interconnect (OIC), OMC delivers significant synergy in terms of maximum performance, reduced SoC design efforts and a lot easier post-silicon debugging/tuning.
OMC is a very small & highly configurable DDR memory controller. It provides very high performance through advanced memory controller design based on proprietary out-of-order scheduling algorithm and high speed implementation technique. Demand for more DRAM bandwidth is getting stronger than ever in a quest to improving user experiences (e.g. higher image resolution). Given the limited amount of physically available DRAM bandwidth, highly efficient memory controller IP is becoming a very critical issue everywhere. With our OMC, SoCs can save significant amount of area & power consumption and meet next generation SoC’s DRAM bandwidth requirements.
OMC is a very small & highly configurable DDR memory controller. It provides very high performance through advanced memory controller design based on proprietary out-of-order scheduling algorithm and high speed implementation technique. Demand for more DRAM bandwidth is getting stronger than ever in a quest to improving user experiences (e.g. higher image resolution). Given the limited amount of physically available DRAM bandwidth, highly efficient memory controller IP is becoming a very critical issue everywhere. With our OMC, SoCs can save significant amount of area & power consumption and meet next generation SoC’s DRAM bandwidth requirements.
特色
- DRAM supports
- JEDEC compliant DDR3/DDR4/LPDDR3/LPDDR4 support
- Up to 4 ranks / channel (configurable)
- High Performance
- Proprietary out-of-order scheduling algorithm
- Dual-PHY control for “2x DRAM channel bandwidth” with single OMC instance
- Low Power Consumption
- Ultra low power consumption with HW controlled dynamic DRAM frequency scaling
- Automatically handles training activities required for frequency change
- Automated low power control of DRAM device
- Special Features
- ECC support
- Security Firewall
- Clock domain split between OMC and PHY for easier timing closure (e.g. in Dual-PHY configuration)
优势
- High Utilization
- +90% DRAM utilization over real-life memory access traces through proprietary out of order scheduling algorithm
- Highly optimized pipeline architecture
- Ultra Low Latency
- Ultra low read latency even at high utilization
- Exceptionally low write latency providing extra performance gain
- Peak latency suppression through proprietary latency-aware scheduling algorithm
- Active QoS Control
- Dynamic priority control based on observed latency & bandwidth for master IPs
- When combined with ORBITTM interconnect (OIC) for maximum performance & flexibility
- Physical-design friendliness
- Support clock domain split between OMC & PHY
- Flexible floorplan of memory controller layout block
- Highly flexible & configurable DDR controller
可交付内容
- IP Core RTL
- Management SW
- Simulation environment
- Detailed Document
应用
- Automotive,
- Application Processors,
- Digital Baseband Modems,
- Set-Top-Box,
- Digital TV,
- OTT,
- Surveillance,
- IoT, Enterprise
- SSD Controllers
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