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Compute Express Link (CXL) 3.0 Controller with AXI
The Rambus Compute Express LinkTM (CXL) 3.0 controller with AXI interface is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe 6.0 controller architecture for the CXL.io protocol and adds the CXL.cache and CXL.mem protocols specific to CXL. The controller supports the AMBA® AXITM Protocol Specification for CXL.io traffic, and either Intel CXLcache/mem Protocol Interface (CPI) or a AMBA® AXI Protocol Specification for CXL.mem and CPI interface for CXL.cache traffic.
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Block Diagram of the Compute Express Link (CXL) 3.0 Controller with AXI
