The AES Standard IP Core provides a simple and compact hardware solution for the Advanced Encryption Standard (AES) block cipher. The Standard IP core comes with a 32-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. The core is designed for applications that need both moderate throughput and reduced power consumption. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.
The AES Standard IP core is available in encrypt, decrypt, and encrypt/decrypt versions.
- Implements AES block cipher specified by NIST FIPS 197
- Synchronous 32-bit IO interfaces
- Integrated key expansion supporting 128, 192, and 256-bit key lengths
- High throughput requires only 44, 52, and 60 clock cycles per encryption
- Small hardware footprint for reduced power consumption
- Quick key wipe for anti-tamper applications
- IPSec, Secure eCommerce (TLS/SSL), WLAN, Digital Rights Management (DRM), Data Storage Encryption (IEEE P1619), Hardware Security Tokens
- Device specific netlist or RTL Verilog/VHDL source code
- Verilog/VHDL simulation model and testbench
- User documentation
Block Diagram of the AES Standard Encryption IP Core