The high-speed ADC series of M31 demonstrates the Tier-1 PPA (Power, Performance, and Area) in the field of the IP industry. By employing innovative circuit techniques, the SAR ADC is able to operate several tens of MHz and beyond thanks to the asynchronous operation, which also saves power a lot. More importantly, the ADC has equal sampling and clock rate which is not commonly seen in conventional SAR ADCs, and also relax the design of PLL/OSC thanks to a reduced clock rate for clock signal distribution.
With the novel CDAC switching technique, the linearity of ADC is enhanced, or the same performance is given under a smaller CDAC size. Needless to say, the technique shows a superior Spurious-Free-Dynamic behavior when the input signal amplitude is low which is especially important as the ADC is to be used in wireless communication to deal with small amplitude wanted signals.
Also, the ADC has a built-in reference buffer that greatly relaxes the driving requirement of the reference source from the SoC top. More than that, by a patented CDAC layout style combined with the aforementioned switching technique, the ADC is TINY (< 50um x 50um, exclude pad, primary ESD clamp). Both features enable the SoC designer to do a more compact design (raises U-rate) and ease the design considerations in integrating ADCs.