New Silicon IP
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DDR5/4 PHY for SS8
- Low latency, small area, low power
- Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
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PHY for PCIe 6.0 and CXL for Samsung SF5A
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HBM2 PHY for Samsung
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PCIe 5.0 PHY for SF5
- Physical Coding Sublayer (PCS) block with PIPE interface
- Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
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PLL_5nm
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PLL_28nm
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PLL_INT_5nm
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LPDDR5X/5/4X PHY on Samsung SF4X
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps
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MIPI D-PHY DSI TX IP
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